The present inventive concept relates to memory devices and related methods of operation. More particularly, the inventive concept relates to methods of operating memory devices by which read errors arising during read operations are reduced.
A NAND flash memory includes memory cells serially connected between a drain selection transistor and a source selection transistor. The number of serially connected memory cells may vary according to the type of the device, the integration density of the memory cells, and other factors.
In conventional NAND flash memory devices, a memory cell may be placed into one of two data states (i.e., programmed) in accordance with corresponding threshold voltage distributions. During a subsequent read operation applied to the memory cell, a single read voltage level is defined between the two threshold voltage distributions, and may be used to discriminate the programmed state of the memory cell. However, in the conventional NAND flash memory devices, coupling due to a parasitic capacitance occurs in each of a plurality of adjacent memory cells arranged along a connecting bit line. The effect of this parasitic capacitance tends to increase the threshold voltage of programmed memory cells. Consequently, accurately discriminating the programmed data state of a memory cell influenced by the parasitic capacitance becomes more difficult, as threshold voltages shift and may ultimately overlap. This is particularly true when a single read voltage level is used, and read errors may arise as a result.